力晶：公告本公司取得日本專利局核發JP 5284737專利

第七條　第8款

1.專利、商標、著作或其他智慧財產權之內容:NONVOLATILE SEMICONDUCTOR MEMORY

DEVICE AND FAIL BIT COUNTING METHOD THEREFOR

2.專利、商標、著作或其他智慧財產權之取得日期:102/06/07

3.取得專利、商標、著作或其他智慧財產權之成本:NT＄ 139,055

4.其他應敘明事項:

The device has a non-volatile memory cell array having several segments

of memory cells in which read-out/writing process of data are

controlled. A control circuit counts the fail bit number generated at

the time of writing or read-out process. The control circuit is

switched by the switches (41-94) according to the data pattern of data,

and the fail bit number is counted so that each region in the

predetermined data length for counting fail bit number is set for every

segment to which data correspond.